S500/Pinmux

From XApple
Jump to: navigation, search

The S500 like many other socs have fewer pads/pins than than the internal logic which provides functionality, this pads can have different functionalities in order to provide more flexibility. The multiplexing is used to alternate the function of the IO pads which are driven by different module. The GPIOs have higher priority than other module functions no matter when they are configured as input or output, when using other module function signal, the OUTEN and INEN of the corresponding GPIOs should be Disable; Otherwise, the module function will be disable


Pin Multiplex Table

BALL GPIO MUX 1 MUX 2 MUX 3 MUX 4 MUX 5 MUX 6 MUX 7
C03 A12 NAND_DQS
D02 A13 NAND_DQSN
H02 A14 RMII_TXD0 SMII_TX SPI2_SCLK UART6_RX PWM4
H03 A15 RMII_TXD1 SMII_SYNC SPI2_SS UART6_TX PWM5
G01 A16 RMII_TX_EN UART2_RX SPI3_SCLK PWM0
H04 A17 RMII_RX_ER UART2_TX SPI3_MOSI PWM1
J04 A18 RMII_CRS_DV SMII_RX SPI2_MISO UART4_RX PWM4
J02 A19 RMII_RXD0 UART2_CTSB SPI3_MISO PWM3
J01 A20 RMII_RXD1 UART2_RTSB SPI3_SS PWM2
G02 A21 RMII_REF_CLK UART4_TX SPI2_MOSI
J03 A22 RMII_MDC
G03 A23 RMII_MDIO
V22 A24 SIRQ0
V21 A25 SIRQ1
U21 A26 SIRQ2
AD16 A27 I2S_D0 NOR_A16
AC16 A28 I2S_BCLK0 NOR_A17 PCM0_IN
AD17 A29 I2S_LRCLK0 NOR_A18 PCM1_SYNC
AC17 A30 I2S_MCLK0 NOR_A19 PCM1_CLK
AB17 A31 I2S_D1 NOR_A1
AD18 B00 I2S_BCLK1 NOR_A21 PCM0_OUT
AC18 B01 I2S_LRCLK1 NOR_A22 PCM0_CLK
AD19 B02 I2S_MCLK1 NOR_A23 PCM0_SYNC
N21 B03 KS_IN0 JTAG_TCK NOR_A5 PWM0 PWM4 SENS1_D4 PWM4
M21 B04 KS_IN1 JTAG_TMS NOR_A6 PWM1 PWM5 SENS1_D5 PWM1
L21 B05 KS_IN2 JTAG_TDI NOR_A7 PWM0 PWM0 SENS1_D6 PWM0
K21 B06 KS_IN3 JTAG_TDO NOR_A8 PWM1 SENS1_D7
J21 B07 KS_OUT0 UART5_RX NOR_A9 PWM2 SENS1_PCLK MMC0_CMD
L22 B08 KS_OUT1 JTAG_TRST NOR_A10 PWM3 SENS1_VSYNC MMC0_CLK
L23 B09 KS_OUT2 MMC0_D1B NOR_A11 PWM2 UART5_TX SENS1_HYNC
B10 B10 LVDS_OEP LCD0_DCLK0
A10 B11 LVDS_OEN LCD0_HSYNC0
C10 B12 LVDS_ODP LCD0_VSYNC0
B11 B13 LVDS_ODN LCD0_LDE0
C11 B14 LVDS_OCP LCD0_D23
B12 B15 LVDS_OCN LCD0_D22
A12 B16 LVDS_OBP LCD0_D21
C12 B17 LVDS_OBN LCD0_D20
A13 B18 LVDS_OAP LCD0_D19
B13 B19 LVDS_OAN LCD0_D15
C14 B20 LVDS_EEP NOR_RD LCD0_D14
B14 B21 LVDS_EEN NOR_WR LCD0_D13
B15 B22 LVDS_EDP NOR_D13 LCD0_D12
A15 B23 LVDS_EDN NOR_D12 LCD0_D11
C15 B24 LVDS_ECP NOR_D11 LCD0_D10
A16 B25 LVDS_ECN NOR_A4 LCD0_D7
B16 B26 LVDS_EBP NOR_D15 LCD0_D6
C16 B27 LVDS_EBN NOR_D14 LCD0_D5
B17 B28 LVDS_EAP NOR_D9 LCD0_D4
C17 B29 LVDS_EAN NOR_D8 LCD0_D3
T19 B30 NOR_A2 SENS1_CLKOUT PWM2 PWM4 LCD0_D18
R19 B31 NOR_A0 MMC0_CLKB MMC1_CMD PWM3 LCD0_D17
A09 C00 DSI_DP3 MMC1_CLKB MMC1_CLK LCD0_D16
B09 C01 DSI_DN3 MMC1_D3 LCD0_D9
B08 C02 DSI_DP1 MMC1_D2 LCD0_D8
C08 C03 DSI_DN1 LCD0_D2
A07 C04 DSI_CP MMC1_D1 LCD0_D1
B07 C05 DSI_CN MMC1_D0 LCD0_D0
A06 C06 DSI_DP0 MMC0_CLKB UART2_RX SPI0_MISO
B06 C07 DSI_DN0 UART2_TX SPI0_MOSI
C06 C08 DSI_DP2 UART2_RTSB SPI0_SCLK MMC1_CLKB
B05 C09 DSI_DN2 MMC1_D1B UART2_CTSB SPI0_SS
Y23 C10 MMC0_D0 NOR_D0 JTAG_TRST UART2_RX UART5_RX
Y2 C11 MMC0_D1 NOR_D1 UART2_TX UART5_TX
V24 C12 MMC0_D2 NOR_D2 JTAG_TDO UART2_RTSB UART1_TX
W23 C13 MMC0_D3 NOR_D3 JTAG_TDI UART2_CTSB UART1_RX
U22 C14 MMC0_D4 NOR_D4 MMC1_D0
V23 C15 MMC0_D5 NOR_D5 MMC1_D1
T23 C16 MMC0_D6 NOR_D6 MMC1_D2
T24 C17 MMC0_D7 NOR_D7 MMC1_D3
W24 C18 MMC0_CMD NOR_A1 JTAG_TMS
W22 C19 MMC0_CLK JTAG_TCK
T22 C20 MMC1_CMD NOR_CEB0_7
U23 C21 MMC1_CLK
AB18 C22 SPI0_SCLK NOR_A12 I2C3_SCLK PCM0_CLK
AC19 C23 SPI0_SS NOR_A13 I2S_LRCLK1 PCM1_OUT PCM0_OUT
AB19 C24 SPI0_MISO NOR_A14 I2S_MCLK1 PCM1_IN PCM0_IN
AA19 C25 SPI0_MOSI NOR_A15 I2C3_SDATA PCM0_SYNC
AC22 C26 UART0_RX UART2_RX SPI1_MISO I2C0_SDATA PCM1_IN I2S_MCLK1
AD22 C27 UART0_TX UART2_TX SPI1_SS I2C0_SCLK SPDIF PCM1_OUT I2S_LRCLK1
AA23 C28 I2C0_SCLK UART2_RTSB I2C1_SCLK UART1_TX SPI1_SCLK
AA24 C29 I2C0_SDATA UART2_CTSB I2C1_SDATA UART1_RX SPI1_MOSI
R22 C31 SENS0_PCLK NOR_A3 PWM0
T21 D10 SENS0_CKOUT NOR_D10 SENS1_CKOUT PWM1
B02 D12 NAND_ALE SPI2_MISO
A02 D13 NAND_CLE SPI2_MOSI
B03 D14 NAND_CEB0 SPI2_SCLK
A03 D15 NAND_CEB1 SPI2_SS
E03 D16 NAND_CEB2 PWM5
C05 D17 NAND_CEB3 PWM4
AC21 D18 UART2_RX
AD21 D19 UART2_TX
AB22 D20 UART2_RTSB UART0_RX
AB21 D21 UART2_CTSB UART0_TX
AD23 D22 UART3_RX
AD24 D23 UART3_TX
AC23 D24 UART3_RTSB UART5_RX
AC24 D25 UART3_CTSB UART5_TX
AA21 D28 PCM1_IN SENS1_D3 UART4_RX PWM4
Y21 D29 PCM1_CLK SENS1_D2 UART4_TX PWM5
AA22 D30 PCM1_SYNC SENS1_D1 UART6_RX I2C3_SCLK
W21 D31 PCM1_OUT SENS1_D0 UART6_RX I2C3_SDATA
AC20 E00 I2C1_SCLK
AB20 E01 I2C1_SDATA
AB23 E02 I2C2_SCLK
AB24 E03 I2C2_SDATA
B01 NAND_D0 MMC2_D0
C02 NAND_D1 MMC2_D1
C01 NAND_D2 MMC2_D2
D01 NAND_D3 MMC2_D3
E02 NAND_D4 MMC2_D4
F03 NAND_D5 MMC2_D5
F02 NAND_D6 MMC2_D6
F01 NAND_D7 MMC2_D7
A04 NAND_RB
B04 NAND_RDB MMC2_CLK
C04 NAND_RDBN MMC2_CMD
A01 NAND_WRB
R23 CSI_DP0 SENS0_D0
R24 CSI_DP1 SENS0_D1
P23 CSI_DN0 SENS0_D2
P22 CSI_DN1 SENS0_D3
N23 CSI_DP3 SENS0_D4
M24 CSI_DP2 SENS0_D5
M22 CSI_DN2 SENS0_D6
M23 CSI_DN3 SENS0_D7
N22 CSI_CP SENS0_HSYNC
N24 CSI_CN SENS0_VSYNC

Although GPIOB[10:19] MUX 2 and GPIOB[20:21] MUX 3 is marked as reserved in the datasheet, in the pin controller driver this function is shown as TS (transport stream).

Other pins

BALL FUNC
D21 PORB
F04 TVCVBS
F22 VCCIO
P19 VDD_CPU_FB
E21 REF_VOL
K24 CLKO_24M
J23 HOSCI
J24 HOSCO
Personal tools
Namespaces

Variants
Actions
Navigation
Tools